Operational Transconductance Amplifier Design

Operational transconductance amplifier is also known as OTA, that converts the voltage input to current output. voltage controlled current source. For this article, we are discussing the differential input single output 2 stage OTA. OTA has a lot of constains in terms of design, it relies on differential amplifier as well as current mirror knowledge. In addition, the stability needs to be taken into considertaion, thus the compensation capacitor should be included, the gain bandwidth would determine some of the mos transconductances. Slew rate, power dissipiation, input common mode range should also be taken into considerations when designing the OTA.

I will refer to various sources of materials for the OTA that are publicly available, so that readers could be able to access the materials instantly. I would refer to one of the most comment notations for the OTA so that it is fairly easy to undertand the equations. In the post for circuit schematic drawing, I used the 2 stage OmAmp as the example, I will provide an other schematic here. Some of the equations are referred from¹ with indexed numbers, like (42.3.6), this means for the 42th episode of a lecture series, the 3rd part of the lecture, equation 6 is the one that we are referring to.

Cadence learning and support library also contains a document named “Operational Amplifier (OpAmp) Stability, CMRR, PSRR, Noise, Slew Rate, THD, Compression Distortion Measurements from ADE Explorer”² regaring OpAmp that I would refer later specifically for Cadence Virtuoso simulations.

https://www.youtube.com/watch?v=hOuBGcZ5m58

https://www.youtube.com/watch?v=96j2tNKFCPI

https://www.youtube.com/watch?v=JqNWyzcZ5bM

tail current, slew rate, equation between tail current, slew rate, compensation capacitor.

In electronics and electromagnetics, slew rate is defined as the change of voltage or current, or any other electrical or electromagnetic quantity, per unit of time

Compensatation capacitor $C_{C}$ is used to deal with the pools created by the high impedance nodes.

$\mu_{n}C_{OX}$ could be calculated by DC analysis with a diode connected load, the current is half the designated tail current, width and length are chosen to be the maximal.

DC analysis for $\mu_{n}C_{ox}$

As the conductance of nmos transistors are calculated, it is time to calculate the width and length ratio, according to the above equation, $\mu_{n}C_{ox}$ value is needed. The diode connected load for the nmos with specific $V_{DD}$ as well as the current source with specific $I_{D}$ is used, at this case the largest width and length for the PDK should be chosen. After doing the DC analysis, the value of betaeffcould be retrieved and $\mu_{n}C_{ox}$ will be obtained.

When setting up the DC analysis on ADE, one needs to make sure the checkbox of save DC Operating Point is clicked.

DC analysis for $V_{TH_{max}}$ and $V_{TH_{min}}$

Gain

The 2 stage OTA has the gain as follows;

The parallel resistance³ $r_{o2} | |r_{04}$ are related to $r_{o2}=\frac{1}{\lambda_{2} I_{D2}}$ and $r_{o4}=\frac{1}{\lambda_{4} I_{D4}}$

Similarly, for the 2nd stage gain $A_{v2}$, the equation is shown as follows:

For node A and B which are drain voltage of $M_{3}$ and $M_{4}$, the $\frac{W}{L}$ for $M_{3}$ and $M_{6}$ is shown as follows:

Gain bandwidth⁴ (42.4), output pole(42.5), RHP zero(42.6)

Input Common Mode Range

Input Commone Mode Range(ICMR) Max/Positive Value⁴(42.7)

Input Common Mode Range(ICMR) Min Value

Threshold Voltage

In the design of OTA, specific minimum and maximum voltage needs to be calculated or simulated, this⁵ and this⁶ shows how the threshold voltage could be figured out using Cadence Virtuoso. The reason behind that is because different levels of ICMR yields various threshold voltages⁷, the test is done in 1st stage amplifier with different ICMR levels.

Design Procedure

Regarding differential input singla output output OTA, the design procedure is shown as follows:

• Smallest device length for constant modulation parameter and good matching for current mirrors.
• Compensation capacitance: 60 degree phase margin $C_{C}>0.22 C_{L}$⁴(42.3.10)
• Tail current: relationship with slew rate.$I=C\cdot \frac{\mathrm{d} V}{\mathrm{d} t}=C\cdot SR$ or based on equation $I_{D_{5}} \approx 10\left(\frac{V_{D D}+\left|V_{S S}\right|}{2 T_{S}}\right)$ with settling time.
• For pmos $M_{3}$, consider ground at source of $M_{1}$, the current of $M_{3}$ should be $I_{D_{3}}=\frac{1}{2} \mu_{P} \operatorname{C_{ox}}\left(\frac{W}{L}\right)_{3}\left[V_{DD}-\left|V_{t h_{3}}\right|-\left(V_{G S_{1}}-V_{t h_{1}}\right)\right]^{2}$, the ratio between width and length could be calculated $\left(\frac{W}{L}\right)_{3}=\frac{I_{D 5}}{\mu_{3} C_{ox}\left(V_{D D}-\left|V_{t h_{3}}\right|-V_{i n}(\text { max })+V_{t h_{1}}\right)^{2}}$. pmos $M_{4}$ has the same width length ratio becasue of current mirror.
• Verify the zeros and poles of $C_{GS_{3}}$ and $C_{GS_{4}}$ are not dominant, GB is gain bandwidth.
• Size of nmos $M_{1}$ and $M_{2}$, 42.3.6, $g_{m_{1}}=GB_{ radiance } \times C_{c}=GB \times 2 \pi\times C_{c}$, $\left(\frac{W}{L}\right)_{1}=\frac{g_{m_{1}}^{2}}{\mu_{n} C_{ox} I_{D_{5}}}$
• Size of nmos $M_{5}$,
• Size of nmos $M_{6}$,
• Current of nmos $M_{6}$: $I_{D_{6}}=\frac{g_{m 6}{ }^{2}}{2 \mu_{p} C_{ox}\left(\frac{W}{L}\right)_{6}}$
• Size of nmos $M_{7}$: $\left(\frac{W}{L}\right){7}=\frac{I{D_{7}}}{I_{D_{5}}}\left(\frac{W}{L}\right)_{5}$
• Power dissipation: $P_{diss}=\left(V_{DD}+\left|V_{ss}\right|\right)\left(I_{D_{6}}+I_{D_{5}}\right)$
• Gain specification check: $A_{v_{calculated}}>A_{v_{ desired}}$

If we take another approach and then put all the essential steps in the following table with respect to each of the cmos transistors, it should be shown as follows.

	$M_{1}$	$M_{2}$	$M_{3}$	$M_{4}$	$M_{5}$	$M_{6}$	$M_{7}$	$M_{8}$	$C_{C}$
$M_{1}$	sat $V_{TH1_{max}}$ $V_{TH1_{min}}$
$M_{2}$		sat
$M_{3}$	$ICMR_{max}$		sat
$M_{4}$			$I_{D4}=\alpha I_{D3}$	sat
$M_{5}$	$ICMR_{min}$				sat
$M_{6}$	$\approx 10\cdot g_{m1}$8		$\approx V_{DS3}$7 $V_{GS3}$7	$V_{DS4}$7 $V_{GS4}$7 $g_{m_{4}}$		sat
$M_{7}$				$\propto I_{D_{4}}$9	$\propto I_{D5}$	$I_{D_{6}}$	sat
$M_{8}$					$\propto I_{D5}$		$\propto I_{D7}$	sat
$C_{C}$	$g_{m_{1}}$	$g_{m_{2}}$			$I_{D_{5}}$10				$0.22C_{L}$

Simulation

DC Operating Point

Setting the differential pair with the same input DC voltage, in ADE L Window Results->Print->DC Operating Points, the parameters can be viewed in the Results Display Window, which is different from annotations. In Results Display Window, parameters like region where 2 stands for saturatoin. If not so, the input DC votlage should be increased.

AC response

AC response of gain and phase is critical for the design regarding the gain and stability of the design.

Gain and Phase: in ADE L Window Results->Direct Plot->AC Gain & Phase, then select output as well as input pins. Unity gain phase margin should be checked. Unity gain performance simulation can be done by connecting negative input to the single end output.¹¹

Slew Rate

CMR Ratio

Power Consumption

Design Example

22nm pdk

As I’m adopting the 22nm PDK, I will try to replicate the design of OTA and show the results form Cadence Virtuoso. For 22nm PDK, the length could be assigned to 20nm, $V_{DD}=0.8V$, load capacitance $C_{L}=90fF$, ICMR max is 0.7V and ICMR min is 0.2V, slew rate $SR=20V/\mu s$, gain bandwidth is 50MHz.

• The compenstion capacitance $C_{C}=0.22\cdot C_{L}\approx 20fF$.
• Tail current $I_{D_{5}}=SR\cdot C_{C}\approx 460nA$, thus $I_{D_{1}}=I_{D_{2}}=230nA$ as we are trying to increase a small portion of the tail current.
• The conductance $g_{m_{1}}=g_{m_{2}}=6.28\mu S$.
• DC analysis of nmos via diode connected structure on Cadence.
• While using ADE Explorer, I’m not able to find the betaeff of nmos and pmos transistors even through I’m able to find other parameters, I will tackle this later but to use the parameters from here¹¹.

45nm GPDK

To refer to the reference¹¹, the GPDK if cadence is used. $V_{DD}=1.2V$, $C_{L}=4pF$, $ICMR_{+}=0.9V$, $ICMR_{-}=0.78V$

• The compenstion capacitance $C_{C}=0.22\cdot C_{L}\approx 1pF$.
• Tail current $I_{D_{5}}=SR\cdot C_{C}\approx 25\mu A$, thus $I_{D_{1}}=I_{D_{2}}=12.5\mu A$ as we are trying to increase a small portion of the tail current.
• The conductance $g_{m_{1}}=g_{m_{2}}=315\mu S$.
• If set width and length of nmos and pmos to 10um, the betaeff for nmos and pmos would be 362.155u and 261.738u.
• Width and length ratio $\left(\frac{W}{L}\right)_{1,2}=10.93$
• Width and length ratio $\left(\frac{W}{L}\right)_{3,4}=0.84$ are related to $ICMR_{+}$, in this case the max threshold voltage needs to be considered.
• Width and length ratio $\left(\frac{W}{L}\right)_{5}=3.12$ based on tail current and $ICMR_{-}$.
• Width and length ratio $\left(\frac{W}{L}\right)_{6}=35.2$ based on $g_{m_{6}}$ and $\left(\frac{W}{L}\right)$.
• Width and length ratio $\left(\frac{W}{L}\right)_{7}=65.35$

1. Inderjit Singh Dhanjal – YouTube[↩]
2. Operational Amplifier (OpAmp) Stability, CMRR, PSRR, Noise, Slew Rate, THD, Compression Distortion Measurements from ADE Explorer, 20495740, 3/30/2021 7:23 AM[↩]
3. Analog VLSI Design Lecture 42.3: Design equations for Two stage OTA – YouTube[↩]
4. Allen, Phillip E., Robert Dobkin, and Douglas R. Holberg. 2011. CMOS Analog Circuit Design. Elsevier.[↩][↩][↩]
5. Design of two stage operational amplifier (opamp) part 7 (design procedure)[↩]
6. Design of Two Stage Operational Amplifier 45nm CMOS Process in Cadence Virtuoso step by step Process[↩]
7. Design of two stage operational amplifier (opamp) part 7 (design procedure)[↩][↩][↩][↩][↩]
8. phase margin $60^{\circ}$[↩]
9. proportional because of $I_{D_{6}}$[↩]
10. $I_{D_{5}}=SR\cdot C_{C}$[↩]
11. Design of Two Stage Operational Amplifier 45nm CMOS Process in Cadence Virtuoso step by step Process – YouTube[↩][↩][↩]